(a) Field of the Invention
The present invention relates to a semiconductor integrated circuit having a substantially equal propagation delay. More specifically, it relates to a semiconductor integrated circuit in which a plurality of logic gates receive a signal fed by a common signal source through respective signal paths of a parallel conductor transmission line, and in which a difference in propagation delay or phase delay caused by the difference in length of the signal paths is eliminated for obtaining a higher signal processing.
(b) Description of the Related Art
In a conventional semiconductor integrated circuit comprising a parallel conductor transmission line in which inputs of a plurality of logic gates are connected through respective signal paths to an output of a single logic signal source, a signal generated by the logic signal source reaches the plurality of logic gates with certain phase delays. The phase delays differ from logic gate to logic gate depending on the length of the signal paths. Various methods have been used to perform synchronous signal processing at the plurality of logic gates regardless of the differences in the phase delay. For example, timing sequence for signal processing at the plurality of logic gates is controlled and shifted depending on the amount of the phase delay at each of the logic gates. In this method, however, the timing control for each of the logic gates is extremely complicated. :Alternatively, the frequency of a timing clock is lowered to allow the logic gates to synchronously carry out the signal processing without being affected by the differences in the propagation delay. In this method, however, a high-speed operation of the semiconductor integrated circuit cannot be obtained.